1. Field of the Invention
The present invention is related to an adder logic circuit for performing an addition operation of numerical values having different bit widths. More specifically speaking, the present invention is related to an improved processor capable of quickly generating addresses necessary to access a memory.
2. Prior Art
Recently, there increasingly arises a great demand for high speed operation of a processor. which is a core element of computer systems, along with an increasing amount of data to be processed such as multimedia application.
A computer system can generally be divided into three basic blocks: a central processing unit (CPU), memory, and an input/output interface (I/O). These blocks are interconnected by one or more buses. Typically. an input device, such as a keyboard, mouse, disk drive, etc., is used to input data and/or computer programs to the computer system through the computer""s I/O device.
The computer programs instruct the computer system as to how the data should be processed. These instructions and data are usually stored in memory. The CPU retrieves the data stored in the memory and processes the data according to the instructions. The results can be stored back into memory or outputted via the I/O interface to a printer, video monitor, speaker, etc.
When a computer program changes a value stored in memory, it is performing a xe2x80x9cstorexe2x80x9d operation. And when the computer is retrieving an instruction or data from memory it is performing a xe2x80x9cloadxe2x80x9d operation. Each of these load and store operations require an address that specifies a location in memory. In a store operation, the address specifies a location in memory that is available for storing the data. In a load operation, the address specifies the location in memory where the desired instruction or data resides.
Typically, in a modern computer system, there are several different varieties of addressing reflecting different levels of abstraction. For example, there are the logical, linear and physical addresses. The logical address is specified in the assembly language or machine code program, and consists of a selector and an offset. The offset is formed by adding together 3 components: base, scaled index and displacement. The logical address space is, therefore, segmented.
The logical address (consisted of segment, offset) is transformed to a flat linear address by adding a segment base corresponding to the segment selector to obtain a linear address.
As mentioned above, a logical address consists of segment: offset pair, and the offset is often itself calculated via a formula as follows.
1) base-register+index-register*scale
2) base-register+immediate.
Correspondingly, this implies that the linear address is
1) segment-base+base-register+index-register*scale
2) segment-base+base-register+immediate.
These formulae and the encodings used to represent them in the instruction stream are called xe2x80x9caddressing modes.xe2x80x9d
Generally speaking, there are a variety of combinations of the two operands as used the addressing modes. For example, the bit width of the first operand may be equal to, or larger or smaller than the bit width of the second operand in each addition operation. Also, the second operand may be either signed or unsigned.
Memory can be divided into one or more variable length segments, which can be swapped to disk or shared between programs. Memory can also be organized into one or more xe2x80x9cpagesxe2x80x9d. Segmentation and paging are complementary. Segmentation is useful to application programmers for organizing memory in logical modules, whereas pages are useful to the system programmer for managing the physical memory of a system.
Typically, a segmentation unit is used to translate the logical address space into a 32-bit linear address space. A paging unit is then used to translate this linear address space into a physical address space. It is this physical address that appears on a microprocessor chip""s address pins.
In the case of accessing an entry within a page, the address of the page is calculated followed by obtaining the physical address by adding the page offset to the address of the page. Also in this case, the bit width of the first operand may be equal to, or larger or smaller than the bit width of the second operand in each addition operation while the second operand may be either signed or unsigned.
In accordance with the prior art, the addition operation of a first numerical value and a second numerical value having a bit width narrower than that of the first numerical value is performed by an adder having the bit width equal to that of the first numerical value after sign-extension or zero-extension of the second numerical value.
For example, as illustrated in FIG. 1, when A[mxe2x88x921:0] and B[nxe2x88x921:01 ] (m greater than n) are added, B[nxe2x88x921:01] is transferred to lower n bits of a latch circuit 101 which has a bit width of m bits followed by transferring the most significant bit B[nxe2x88x921] to all the remaining higher bits of the latch circuit 101. On the other hand, A[mxe2x88x921:0] is transferred to a latch circuit 103 which has a bit width of m bits. These two m-bits values are added by means of the m-bit adder 105 in a usual way.
However, as explained above, the addition operation is frequently performed when accessing to a memory. For example, while call or jump procedures relative to next instruction appears in most loops, the extension process is also repeated in the loops resulting in significant influence upon the performance of the system.
The present invention has been made in order to solve the shortcomings as described above. It is an important object of the present invention to provide an adder logic circuit capable of performing an addition operation of a first numerical value and a second numerical value having a bit width narrower than that of the first numerical value at a high speed.
It is another object of the present invention to provide an improved processor capable of quickly generating addresses necessary to access a memory.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved adder logic circuit for performing an addition operation of a first numerical value and a second numerical value having a bit width narrower than that of said first numerical value comprising:
an adder element for performing an addition operation of said second numerical value and a third numerical value composed of a lower bit sequence of said first numerical value, the bit width of said third numerical value being equal to the bit width of said second numerical value; and
a higher bit handling logic circuit connected to said adder element for receiving a carry out from the most significant bit of said adder element together with a fourth numerical value composed of a higher bit sequence composed of the remainder of said first numerical value, the most significant bit of said the second numerical value in order to output one of said fourth numerical value, said fourth numerical value as incremented and said fourth numerical value as decremented in accordance with the carry out from the most significant bit of said adder element and the most significant bit of said second numerical value.
Also, in accordance with a preferred embodiment of the present invention. said higher bit handling logic circuit is composed of an incrementer for incrementing said fourth numerical value, a decrementer for decrementing said fourth numerical value and a selector logic circuit for outputting one of the output of said incrementer, the output of said decrementer and said the fourth numerical value in accordance with the most significant bit of said second numerical value.
Furthermore, in accordance with a preferred embodiment of the present invention, said selector logic circuit Is composed of a first selector element for selecting and outputting one of first and second pairs of bit sequences in accordance with the most significant bit of said second numerical value, the first pair comprising the output of said incrementer and said fourth numerical value, the second pair comprising the output of said decrementer and said fourth numerical value, and a second selector logic circuit for selecting and outputting one of the pair as selected by said first selector element in accordance with the carry out from the most significant bit of said adder element.
In accordance with another aspect of the present invention, a processor including:
an address bus connected to a memory;
a data bus connected to said memory; and an address generating unit for calculating an address of an instruction/data required for execution of a program;
said address generating unit provided with an adder logic circuit for performing an addition operation of a first numerical value and a second numerical value having a bit width narrower than that of said first numerical value, said adder logic circuit comprising;
an adder element for performing an addition operation of said second numerical value and a third numerical value composed of a lower bit sequence of said first numerical value, the bit width of said third numerical value being equal to the bit width of said second numerical value; and
a higher bit handling logic circuit connected to said adder element for receiving a carry out from the most significant bit of said adder element together with a fourth numerical value composed of a higher bit sequence composed of the remainder of said first numerical value, the most significant bit of said the second numerical value in order to output one of said fourth numerical value, said fourth numerical value as incremented and said fourth numerical value as decremented in accordance with the carry out from the most significant bit of said adder element and the most significant bit of said second numerical value.
In accordance with a further aspect of the present invention, a processor including:
an address bus connected to a memory;
a data bus connected to said memory; and
an address generating unit for calculating an address of an instruction/data required for execution of a program;
said address generating unit provided with a first adder logic circuit for performing an addition operation of two numerical values having the same bit width and a second adder logic circuit for performing an addition operation of a first numerical value and a second numerical value having a bit width narrower than that of said first numerical value, said adder logic circuit comprising:
an adder element for performing an addition operation of said second numerical value and a third numerical value composed of a lower bit sequence of said first numerical value, the bit width of said third numerical value being equal to the bit width of said second numerical value; and
a higher bit handling logic circuit connected to said adder element for receiving a carry out from the most significant bit of said adder element together with a fourth numerical value composed of a higher bit sequence composed of the remainder of said first numerical value, the most significant bit of said the second numerical value in order to output one of said fourth numerical value, said fourth numerical value as incremented and said fourth numerical value as decremented in accordance with the carry out from the most significant bit of said adder element and the most significant bit of said second numerical value.